1. Field of the Invention
The present invention relates to a semiconductor apparatus comprising a plurality of wiring layers, a method of manufacturing the semiconductor apparatus, and a wiring device for the semiconductor apparatus.
2. Description of the Related Art
In a semiconductor apparatus in which a plurality of transistors is mounted, variations in its property and structure more remarkably affect a drive performance of each transistor as miniaturization is advanced. Examples of the variations include a variation resulting from a fluctuation of a power-supply voltage and a variation in manufacturing the transistors, which largely changes the drive performance of each transistor. Such problems is generated due to the foregoing disadvantage that a device which satisfied timing restrictions in a designing stage and was expected to normally operate consequently fails to satisfy the timing restrictions when actually manufactured, and as a result, is unable to execute any desired operation.
In order to avoid such a design error, it is important to secure a sufficient design margin in consideration of the variations when the semiconductor apparatus is manufactured. There is a hold time of a flip-flop as an example of the design margin, which is a minimum time length in which a data signal must be retained after a clock signal is inputted to the flip-flop. If it is not possible to retain the data signal during the minimum time length, the flip-flop consequently retains incorrect data, which causes a malfunction. Therefore, it is necessary to take account of the design margin (hold time in this case) so that correct data can be retained in the flip-flop even though the drive performance of the transistor is varied due to the foregoing variations so that arrival times of the clock and data are changed.
FIG. 15 shows a conventional semiconductor apparatus 1000. The semiconductor apparatus 1000 comprises flip-flops 1010 and a scan chain 1020 for implementing a scan test. A reference symbol SI denotes a terminal of the flip-flop 1010 for retrieving scan data. As recited in No. 2004-301661 of the Japanese Patent Applications Laid-Open, a wiring layer having a resistance value per unit length higher than that of a wring layer in which a wiring of the clock signal is formed is adopted for the scan chain 1020 in order to satisfy the hold time at the SI terminal.
Even though a signal propagation time in the scan chain 1020 that connects the flip-flops provided in vicinity to each other is changed due to the before-mentioned variations, the hold time in the SI terminal can be thereby satisfied as a sufficient delay value is obtained by use of the higher-resistance wiring.
However, it is inadequate to provide the wiring layer having the higher resistance value per unit length in such a signal line where a critical signal speed is demanded. In order to deal with the disadvantage, it is necessary that the higher-resistance wiring layer is formed so as to avoid such a signal line.
According to the foregoing method, however, connection spots are increased with respect to wiring layers located up and down the higher-resistance wiring layer, and thereby congestion of the wirings is generated. When the wirings are congested, circumvention of the wirings or crosstalk between the adjacent wirings each other is generated, which makes it impossible to satisfy the timing restrictions in the signal line in which the critical signal speed is demanded. As a result, it becomes difficult to operate the semiconductor apparatus at a desired operation frequency.